1. Field of the Invention
The invention relates to an ATM interface device and method of using the device for a data transmission between a first ATM device and a second ATM device.
2. Description of the Related Art
The significance of transmission and switching technologies for high data transmission rates (greater than 100 Mbit/s) is increasing due to the increasing need for a transmission of video information in modern communications technology such as, still and moving images in picture telephony applications or the display of high-resolution graphics at modern personal computers. The asynchronous transfer mode (ATM) is a known data transmission method for high data rates. A data transmission on the basis of the asynchronous transfer mode currently enables a variable transmission bit rate of up to 622 Mbit/s.
Known switching equipment, including those that operate on the basis of the asynchronous transfer mode, are usually modularly constructed. A backplane (a central plug assembly shared by all assemblies) connects a plurality of assemblies, including an interface for the connection of subscriber lines, and a central controller or a through-connection mechanism. The modularity of the switching equipment that is achieved in this configuration enables, among other things, an easy adaptation of a switching equipment to different configurations as well as a simplified error analysis when servicing the equipment.
The data sheet xe2x80x9cMOS INTEGRATED CIRCUIT xcexcPD98410xe2x80x9d, NEC Corporation, 1997, Document No. S12624EJ1V0DS00 (1st Edition) discloses an LSI through-connect module that allows an addressing of a plurality of interfaces via a 16-bit wide, high-frequency ATM-specific bus interface the (UTOPIA interface: Universal Test and Operations PHY Interface for ATM).
For using such a through-connect module designed for ATM applications in a through-connect module of an ATM switching equipment, it has already been proposed that the through-connect module be placed on the central plug assembly. A conversion of the 16-bit wide data bus onto a plurality of 8-bit wide unidirectional data busses is realized by ATM multiplex devices connected to the through-connect module via a 16-bit wide data bus, so that traditional, 8-bit wide modules can be employed on the assemblies.
The Data Sheet xe2x80x9cMPC860SARxe2x80x94Functional Design Specificationxe2x80x9d, Motorola, 6/97 discloses a control module MPC860SAR that comprises an 8-bit wide, bidirectional ATM-specific bus interface (UTOPIA interface), that could be used for example, for a connection of a central control assembly to an ATM switching equipment.
Both the ATM multiplexer as well as the control module MPC860SAR realize an access coordination for data busses connectable to them, i.e., the ATM multiplexer and the control module MPC860SAR are xe2x80x9cmasterxe2x80x9d modules for the 8-bit wide data busses connectable to them.
European Patent EP 0 492 440 discloses an ATM interface device via which a data communication between two ATM devices is realized upon intermediate storage of the communicated data in a FIFO memory (First In First Out). An inscription or, respectively, readout of data from the FIFO memory ensues with an activation of the FIFO memory by a read or, respectively, write signal sent from an ATM device.
The present invention is based on the object of specifying a method and an arrangement with which a data transmission can be realized between a first and a second ATM device respectively configured as xe2x80x9cmasterxe2x80x9d.
This object is achieved by a method for a data transmission between a first ATM device and a second ATM device via an ATM interface device, wherein the first ATM device comprises a data-transmitting ATM transmission module and the second ATM device comprises a data-receiving ATM reception module, comprising the steps of:
communicating, by a control module of the ATM interface device, a first receiver status information for signalling free memory capacity of a memory of the ATM interface device to the ATM transmission module;
activating a first memory control input of the memory by the ATM transmission module and outputting the data to be communicated by the ATM transmission module onto a first data bus connecting the ATM transmission module to the memory;
intermediately storing data received via the first data bus by the memory as long as the first memory control input is activated;
communicating, by the control module, to the ATM reception module, a sender status information for signalling a presence of data to be communicated from the memory to the ATM reception module;
activating, by the control module, a second memory control input of the memory when the ATM reception module is ready to receive and when data to be communicated to the ATM reception module are intermediately stored in the memory;
outputting, by the memory the intermediately stored data onto a second data bus that connects the memory to the ATM reception module, as long as the second memory control input is activated.
The object is also achieved by an ATM interface device, comprising:
at least one first data bus for connection to a first ATM access control device that implements an access coordination of the first data bus;
at least one second data bus for connection to a second ATM access control device implementing an access coordination of the second data bus;
a first memory for an intermediate storage of data to be communicated from the first access control device to the second access control device, the first memory comprising:
a first memory control input that is driven by the first ATM access control device such that, given activation of the first memory control input, a storing of data communicated from the first ATM access control device ensues, and
a second memory control input that is driven by the second ATM access control device such that, given activation of the second memory control input, a communication of data stored in the first memory ensues to the second ATM access control device,
the ATM interface device further comprising:
a second memory for an intermediate storage of data to be communicated from the second ATM access control device to the] first ATM access control device, the second memory comprising:
a first memory control input that is driven by the second ATM access control device] such that, given activation of the first memory control input, an inscription of data communicated from the second ATM access control device ensues, and
a second memory control input that is driven by the first ATM access control device such that, given activation of the second memory control input, a communication of data stored in the second memory ensues to the first ATM access control device,
the ATM interface device further comprising:
a control module for determining free memory capacities of the first memory and of the second memory and for communicating:
a receiver status information for a signalling of free memory capacity of the first memory to the first ATM access control device,
a second receiver status information for signalling free memory capacity of the second memory to the second ATM access control device
a first sender status information to the first ATM access control device for a signalling of a presence of data to be communicated from the second memory to the first ATM access control device, and
a second sender status information to the [the] second ATM access control device for signalling a presence of data to be communicated from the first memory to the second ATM access control device.
A critical advantage of the invention is that both the first as well as the second ATM device continue to be configured as xe2x80x9cmasterxe2x80x9d device for the data bus connected to them, so that only minor modification of xe2x80x9chardware structurexe2x80x9d of the respective ATM device are required.
A further advantage of the invention is that, due to an interposition of an ATM interface device that is connected via a first data bus to a first ATM device and via a second data bus to a second ATM device, conflicts that might occur for a simultaneous access of the first and of the second ATM device to a data bus connecting them are avoided.
A time decoupling of the first and second data bus is realized by an intermediate storage of communicated data in the ATM interface device so that the two data busses can be operated with a separate clock rate different from one another.
Advantageous developments of the invention are described below.